Mizanur Rahaman Nayan
Nanoelectronics Research Lab. Georgia Tech. GA. USA.
Pettit Microelectronics Building (C2-60)
791 Atlantic Dr NW
Atlanta, GA 30332
I am a PhD student in the Nanoelectronics Research Lab at Georgia Tech, working under the supervision of Professor Azad J. Naeemi.
My PhD research focuses on addressing memory wall impact in computing systems while serving emerging applications e.g., Modern and Classical AI, Large Scale Search through cross layer design approach. I focus on holistic approach for innovation and integration across technology, circuit, micro architecture and computational modeling for effective and efficient workload executions, enabling memory centric computing unlike conventional computing system.
I am driven by a passion for technological innovation, aiming to develop solutions that not only address current challenges but also lay the groundwork for a more sustainable and intelligent future.
news
| Jun 01, 2026 | Joining Sk hynix America as an Intern for Summer! |
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| May 05, 2026 | Successfully completed the Ph.D. Candidacy Exam. |
| Mar 31, 2026 | Selected as a DAC Young Fellow. |
| Jun 30, 2025 | First authored paper titled, “HyDra: A SOT-CAM based vector symbolic macro for HDC” got accepted in ICCAD 2025! |
| Jun 23, 2025 | Presented Research Poster in DAC 2025. |
| May 17, 2025 | Joining Nissan Advanced Technology Center as ML Hardware Accelerator Research Intern! |
| Nov 19, 2024 | First authored paper, ‘Axon’ has been accepted for DATE’25 to be held at Lyon, France! |
| Aug 30, 2024 | Awarded Center for Research into Novel Compute Hierarchies(CRNCH) Ph.D. Fellowship |
| Aug 01, 2024 | Journal Paper Accepted at Wiley International Journal of Circuit Theory and Applications, Paper Link |
| Jan 11, 2024 | Awarded Silicon Creation Grant for ISSCC’24 |
selected publications
- ICCAD 2025HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing2025 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2025
- DATE 2025Axon: A novel systolic array architecture for improved run time and energy efficient GeMM and Conv operation with on-chip im2col2025 Design, Automation & Test in Europe Conference (DATE), 2025
- Wiley IJCTAFrequency tunable CMOS ring oscillator-based Ising machineInternational Journal of Circuit Theory and Applications, 2024
- IEEE ICECEA Deep Ensemble Model with an Efficient Feature for Multi-class Arrhythmia Classification Utilizing 12-Lead ECG SignalIn , 2022
- IEEE APSIPA ASCParallel Training of TN and ITN Models Through CycleGAN for Improved Sequence to Sequence Learning PerformanceIn , 2022
- IEEE ICECE